What is 3CMemory?
How does 3CMemory compare to other forms of DRAM?
What are the unique parts that make up 3CMemory?
What is a modified differential pair?
What is a current controller?
Why is 3CMemory able to use a standard CMOS process?
What is the reason for 3CMemory's improvement in noise sensitivity?
How does the current stop feature reduce the power consumption in 3CMemory?
How does 3CMemory read a multi-bit cell?
How does 3CMemory compare in size to other DRAMs in the industry?
What is the status of the 3CMemory proof of concept test chip?
How much power savings can be expected by implementing 3CMemory?
What is a typical voltage swing on the read bit line for 3CMemory? Write bit line?
What is the status of the patent for 3CMemory?
What is 3CMemory?
3CMemory is silicon based DRAM. The name 3CMemory stands for 'Clocked Current Controlled Memory.' 3CMemory takes a fresh look at solving the DRAM problem from the ground up by re-architecting the memory system with a creative and novel bit cell.
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How does 3CMemory compare to other forms of DRAM?
The 1T memory architecture has been the standard for DRAM for many years. Nevertheless, the 1T architecture has several drawbacks. The high capacitance bit lines have full scale digital voltage transitions on them. This causes high power usage. The 1T architecture has a destructive read process. During the read process, the charge stored on the bit cell is lost due to the charge share process and must be restored. This requires extra clock cycles slowing the read cycle time. The charge sharing process also reduces the available read signal making the memory system more susceptible to noise.
3CMemory eliminates the drawbacks of the 1T architecture. With 3CMemory there is no large signal swing on the high capacitance bit lines which saves a lot of power. There is no destructive read process so there is no need to restore the charge on the bit cell after every read, thus saving clock cycles and shortening the total read cycle time. Also, since 3CMemory doesn't use the 1T charge sharing process, it does not suffer from the large attenuation in the read signal as does the 1T architecture. Therefore, 3CMemory will be much less sensitive to noise.
There are other advantages to 3CMemory. 3CMemory offers the advantage of using a standard CMOS process with no extra processing steps or special capacitors. This makes it easy to use 3CMemory as embedded DRAM.
3CMemory offers a simplified design process.
As to the advantages of 3CMemory over the 3T architecture in prior art, the uncertain effect of the hold node transistor threshold voltage is cancelled by using a differential pair construct. Eliminating the unpredictable aspect of the threshold voltage on the current controlling the read bit line allows increased predictability and finer control of this current. Therefore, smaller logic voltage intervals can be used causing less power dissipation and/or a longer time between storage capacitor refreshes, which also reduces power.
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What are the parts that make up 3CMemory?
3CMemory has one or more bit cells, both read and write bit lines, a differential bit line amplifier, a reference voltage generator, and a logic decoder.
It also has constructs known as a modified differential pair and current controller which are defined below.
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What is a modified differential pair?
The bit cell for 3CMemory is based on the principle of a so-called modified differential pair. A modified differential pair has two transistors operating as a standard differential pair. However one of the transistors has its source buffered with a unity gain configured opamp. This buffered transistor can then drive many other transistors at the same time, effectively making several differential pairs driven from the same transistor.
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What is a current controller?
In the context of 3CMemory, a current controller is a structure that uses a modified differential pair to control the current in the bit cell. The current in the bit cell controls the voltage on the bit line.
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Why is 3CMemory able to use a standard CMOS process?
The biggest reason 3CMemory can use a standard CMOS process is because the 3CMemory bit line signal is independent of the ratio between the bit line capacitance and the storage capacitance in the bit cell.
Therefore, since it is not critical to absolutely maximize the storage capacitor to maintain some reasonable level of read signal, a standard CMOS process can be used and 3CMemory can be more easily embedded into the rest of the system.
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What is the reason for 3CMemory's improvement in noise sensitivity?
The current controller causes gain instead of attenuation in the read bit line signal.
In 3CMemory, the read bit line signal changes as the square of the bit cell voltage and also increases with time. In existing 1T memory, the read bit line signal is changed by multiplying the bit cell voltage by a number much less than one.
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How does the current stop feature reduce the power consumption in 3CMemory?
When determining the value of the memory the important information is in the initial significant moving of the read bit line voltage. The current stop feature stops the read bit line from changing by stopping the current in the bit cell at the first point after the read bit line voltage change is deemed significant and long before the inherent limit due to circuit topology is reached.
The voltage transitions on the high capacitance read bit lines are drastically reduced because the signal on the read bit lines needs to change only enough to be sensed reliably. In this way, power is correspondingly reduced for all reads of the memory system.
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How does 3CMemory read a multi-bit cell?
3CMemory uses multiple references in multiple comparisons to determine the memory value. The references are compared to the storage capacitor voltage sequentially while the read bit line is monitored for the first change in voltage.
The point in the sequence of comparisons that the read bit line first changes as a result of a comparison indicates the value stored on the storage capacitor.
For example, assume seven values, value1, value2, value3, value4, value5, value6 and value7 where value1 is the smallest and value7 is the largest. The memory contains one of four values: value1, value3, value5 or value7. The references used for comparison are value2, value4 and value6. The steps in the read comparisons are:
1. First comparison is to value6. Is the memory value larger than value6?
Yes, and the voltage on the bit line starts changing. Therefore, the memory is value7. DONE.
No, and the voltage did not change. The memory is not value7. Make the next comparison.
2. Second comparison is to value4: Is the memory value larger than value4?
Yes, and the voltage on the bit line starts changing. Therefore, the memory is value5. DONE.
No, and the voltage did not change. The memory is not value5 either. Make the next comparison.
3. Third comparison is to value2: Is the memory value larger than value2?
Yes, and the voltage on the bit line starts changing. Therefore, the memory is value3. DONE.
No, and the voltage did not change. Therefore, the memory is value1. DONE.
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How does 3CMemory compare in size to other DRAMs in the industry?
3CMemory is competitive in terms of area with other DRAMs on the market.
The following floor plans were done to give accurate size estimates for using 3CMemory in a larger array:
1. TSMC 0.18um SCMOS Rules - 800Kbit
Size: 3.1mm x 2.4mm
2. Commercial 0.13um process - 800Kbit
Size: 1.65mm x 1mm
3. Commercial 0.13um process - 10Mbit
Size: 13.3mm x 1.3mm
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What is the status of the 3CMemory proof of concept chip?
The theoretical concepts in the 3CMemory have been converted to schematics and the puzzles have been solved to convert them to layout.
A proof of concept chip database has been created that has all of the blocks necessary to make a large memory array. The blocks have all been designed and laid out. The design was done in a TSMC 0.18um process using scalable CMOS rules. The design is an 8K bit DRAM. It has 2 banks with 64 rows of 8-bit words by 8 columns.
The design is LVS and DRC clean.
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How much power savings can be expected by implementing 3CMemory?
3CMemory users can expect to save about 90% of the power compared to a 1T architecture.
Power calculations and estimates are here.
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What is a typical voltage swing on the read bit line for 3CMemory? Write bit line?
Typically, using the current stop feature on a 0.13um process, the voltage transitions on the high capacitance read bit lines would be 0.2V. For the write bit lines, the voltage swing would be data dependent but would average 0.5V.
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What is the status of the patent for 3CMemory?
3CMemory is patent pending with a priority date of Feb. 20, 2009. The publication date was Dec. 16, 2010.
The patent application number is US 2010/0315858. The title is 'Memory Architecture with a Current Controller and Reduced Power Requirements.'
The abstract is as follows:
Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold.
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