3CMemory-Test Chip

All Necessary Cells to Make a Large Memory Array Are Designed

Test chip is an 8K DRAM with 2 banks. Each bank has 64 rows by 8 columns of 8-bit words.
The design is a TSMC 0.18um process using scalable CMOS rules.
Design, simulation and layout database are complete.
Database cells are transferable to larger memory arrays.